What is Standard Cell Library

 A standard cell library is a collection of well-defined and appropriately characterized logic gates that can be used to implement a digital design by paying attention to the cell height, cell width, voltage rails, well definition, pin placement, and Metal layers, etc.

What cells are there in a standard cell library?

• Combinational logic cells (NAND, NOR INV, etc)
• variety of drive strengths for all cells
• complex cells like AOI, OAI, etc
• Fanin <= 4
• Eco cells

Since each of them comes with a variety of drive strengths so we have to feed with the output buffers or inverters that are inside the cell i.e. there could be some sort of inverters or buffers or some transistors inside the cell and we provide different widths of these outputs to be able to drive higher and higher output capacitance so we will have lots of those, they are usually called like X1, X2, X3, etc. and so forth it describes the size of the relative size of these cells.

• Buffers / Inverters
• Large variety of drive strength
• to mitigate over the delays
• "Clock cells" with balanced rise and fall delays
• to minimize the skew over we build the clock tree
• Delay cells
• usually used for hold fixing
• Level Shifters
• helps to communicate between multiple supply voltages across the different voltage domains.
• Sequential cells
• Many types of flip-flops with posedge/negedge, set/reset, q/qb, enable
• Latches
• Integrated Clock gating cells
• Scan enable cells for ATPG (Automatic Test Pattern Generation)
• Physical Cells
• Filler cells; Tap cells; Antennas cells; Decap cells; Tie cells

Note 1: Multiple Drive Strength:-

• Each cell will have various-sized output stages.
• Larger output stage ---> better at driving fanouts/loads but posses more leakage
• Smaller drive strength ---> less area, less leakage, input cap
  

Note 2: Multiple Threshold:- 

• A single additional mask can provide more or less doping in a transistor channel, shifting the threshold voltage.
• Most libraries provide equivalent cells with three or more VTs: SVT, LVT, and HVT. This enables the tradeoff between speed and leakage.
• All threshold varieties may have the same footprint and therefore can be swapped without any placement or routing iterations.

Note 3: Clock Cells:-

General standard cells are optimized for speed.

                                               min. tpd = min (tplh + tphl) / 2     =/= tplh / tphl

this is not good for clock nets.

• Unbalanced rising/falling delays will result in wanted skew.
• Special "clock cells" are designed with balanced rising-falling delays to minimize skew. These cells are usually less optimal for data and so should not be used.

See "Propagation Delay is usually defined as the average of the low to high and high to low transition of a cell" When we minimize and try to make a perfect cell we get some sort of a beta ratio between pullup and pull down or CMOS cells but it does not mean that we get equality here between the low to high and high to low transition. So, balanced cells are not necessarily the fastest cells and usually what we have in standard cell libraries, in general, is the fastest cell that we can make however that's really bad for clock nets when we have unbalanced rising and falling delays, we get unwanted skews. So, that's why we have a special clock cell that is designed with balanced rising and falling delays.

Usually don't want to use these cells during your std. logic synthesis because they don't optimize for speed.

In general, only buffers/inverters should be used on clock nets. But sometimes we needed the gating the logic by using a special cell such as "integrated clock gates" which provide the defined logic for the clock network and save our losses occurring also prevent from undriven clocks to any network.

        These integrated clock gates cells are provided in our library (.lib) and they are also going to be optimized to be balanced.

Note: Level Shifters: Level shifter cells are placed between voltage domains to pass signals from one voltage domain to another domain.

• HL (high to low) level shifter-
• Requires only only one voltage
• Posses singe height cell

• LH (low to high) level shifter-
• Needs 2 voltages
• Often posses the double height
• So they take up the two standard cell rows.

Physical only cells:-

1. Filler cells- 

• Filler cells have no logical connectivity, these cells are provided continuity in the rows for VDD and VSS nets.
• It ensures the well and diffusion mask continuity.
• Provides the dummy poly for the scaled technologies.
• The IC Compiler II tool supports filler cells with and without metal and supports both single-height and multi-height filler cells.

Note- If nwell is discontinuous the DRC rule will tell that place cells further apart i.e maintain the minimum spacing because there is a well proximity effect.

Well proximity effect: -

During the manufacturing of chips, we will get these types of problems, that's why they are second-order effects. In this, the transistors that are close to the well edge have different performance than ideally placed transistors, because of this effect the transistor speed can vary by +- 10%. 

The transistor placed to the well boundary so it will get many problems during ion implantation. Implanted ions are coming to the well boundary and reflected/scatter from the well boundary to transistors Q1 & Q5 boundary and ions are deposited on the  Q1 Q5 boundary. Ion particles are scattered/reflected due to photoresist on both side of nwell wall, these ions are deposited only those transistors who are near to the well boundary, so any one of the terminals of transistors gets affected by ion implantation and the rest of the transistor will get uniform ions.

2. Decap Cells- Some standard cell libraries have end cap cell which serve as decap cell also. 

Actually, this type of capacitor will clean any type of noise. We can do that just by sticking the capacitor in these filler cells and also we can do that with different types of moscaps, we call these cells as D capsules.

This decap cells do supply the required power to the power-hungry cells as well. 

3. End-cap cells- Also called as Boundary cells". The end cap cell or boundary cell is placed at both the ends of each placement row to terminate the row. It has also been placed at the top and bottom row at the block level to make integration with other blocks. So, that it make the proper alignment with the other block.

Boundary cells have fixed attributes therefore, these cells cannot be moved during the optimization.

The end cap cells are placed in the design because of the following reasons:

·       To protect the gate of a standard cell placed near the boundary from damage during manufacturing.

·       To avoid the base layer DRC (Nwell and Implant layer) at the boundary.

Criteria for placing it is- Boundary cells are placed just after the macro placement and site row creation. Boundary cells are placed before the placement of standard cells and therefore it is called a pre-placed cell.

WellTap cells with criteria to place: -

Well tap cells (or Tap cells) are used to prevent the latch-up issue in the CMOS design. Well-tap cells connect the nwell to VDD and p-substrate to VSS to prevent the latch-up issue.

·       Well tap cell has no input and output pins; therefore, it is called a physical-only cell.

·       Tap cells are placed in regular intervals in standard cell row and distance between two tap cells given in the design rule manual (.lib).

·       Well Tap cells are usually placed on the power rails of the std. cells.

·       Before global placement (during the floor planning stage), you can insert tap cells in the block.

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