Logical Synthesis:- Synthesis is the process that converts a RTL into a technology specifying gate-level netlist, optimized for a set of pre-defined constraints. Inputs- rtl design, std. cell library and a set of design constraints Output- a gate-level netlist, mapped to the std. cells library (.lib file) Note: For fpga's: lut, flip flops and RAM blocks are been obtained and given as the inputs in the further steps. Hopefully, it is also efficient in terms of speed, area, power, etc. figure 1 What is Logic Synthesis? ...
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