Logic Synthesis

Logical Synthesis:-

Synthesis is the process that converts a RTL into a technology specifying gate-level netlist, optimized for a set of pre-defined constraints.

Inputs- rtl design, std. cell library and a set of design constraints

Output- a gate-level netlist, mapped to the std. cells library (.lib file)

Note: For fpga's: lut, flip flops and RAM blocks are been obtained and given as the inputs in the further steps. Hopefully, it is also efficient in terms of speed, area, power, etc.


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What is Logic Synthesis?


                                                                        figure 2

Why perform logic synthesis?

Ans- It automatically manages many details of the design process:

  • Fewer bugs
  • Improves productivity
  • Abstract the design data (HDL description) from any particular implementation technology
  • Design can be re-synthesized targeting different chip technologies. E.g.: first implement in fpga then later in ASIC
  • In some cases, leads to a more optimal design that could be achieved by manual means (eg: logic optimization)
Why not Logic Synthesis?
Because it may lead to less-than-optimal designs in some cases.

Goals of Logic Synthesis:-
1. Minimize Area- in terms of literal count, cell count, register count, etc
2. Maximize Performance- In terms of the maximal clock frequency of synchronous systems, throughout asynchronous systems.
3. Minimize Power- In terms of switching activity in the individual gates, deactivated circuit blocks, etc
4. Any Combinational of the above-
  • Combined with different weights
  • Formulated as a constraint problem
    • Minimize area of a clock speed > 300MHz
5. More global objecgtives-
Actual physical sizes, delays, placement and routing easily.

How does it works?
Variety of general and ad-hoc methods are taken-
  • Instantiation: Maintains a library of primitive modules (AND, OR, NOT) and user-defined modules.
  • Macros expansion/substitutions: A large set of language operators (+, -. boolean operators, etc) and constructs (if_else, case) expand into special circuits.
  • Interference: Special patterns are detected in the language description and treated specially. Eg: inferring memory blocks from the variable declaration and read/write statements, fsm detection and generation from always@(posedge clk) blocks.
  • Logic Optimization: Boolean operations are grouped and optimized with logic minimization techniques.
  • Structural Reorganization: Advanced Techniques including sharing of operators and retiming of circuits (moved FFs) and other.
Basic Synthesis Flow:-

  • Syntax Analysis: Read the hdl files and check for syntax errors. a command is-    read_hdl -verilog sourcecode/toplevel.v 

  • Library Definition: Provide standard cells and IP libraries. It tells what are technologies, and what are the leaf cells (in other words is that what type of IP it has). command is-    read_libs "/design/data/my_fab/digital/lib/TT1V25C.lib"

  • Ellaborate and Binding: This is actually the first step of synthesis which is when we convert the RTL into a boolean structure and then we start running all kinds of optimizations according to computational boolean algebra, all kinds of state reduction encoding register inferring and when we reach all kind of leaf cells then we don't know what to do, it is such as an IP like an SRAM block or an io cells or some sort of analog block and also when we run into things like instantiate, it send ourselves what we have to do is binding them.
    • Convert RTL into a Boolean structure
    • State Reduction, encoding, register to infer
    • Bind all leaf cells to provide libraries
    • A command can also describe what your top-level module is- elaborate toplevel
  • Constraint Definition: Define Clock frequency and other design constraints. In general, we usually use a format called SDC (Synopsis Design Constraints) even though there is another way of defining constraints so we use the command such as read_sdc and point to the SDC file to define those.
  • Pre-Mapping Optimization: Map to generic cells and perform additional. We take the boolean logic that we have elaborated with our binding and map to these generic cells that are internal to the tool which represent a kind of std. cells that it would generally find in a library and do all kinds of heuristics and optimizations on that. command- syn_generic
  • Post-mapping Optimization: Iterate our design, changing gate sizes, boolean literals, and architectural approaches to try and meet constraints. command- syn_opt
  • Report and Export: Report the final result with an emphasis on timing reports, area reports, etc. command- report_timing -num paths 10 > reports/timing_reports.rpt
    • Exporting netlist and other results for further use (which would be considered as an idea as per the gate_level netlist of the synthesis stage). command- write hdl > export/netlist.v

                                                                        figure 3

Synthesis vs Compilation
Before starting the synthesis, we need to check the syntax for correctness i.e. called to be "compilation".

Compiler- 
  • Recognizes all possible constructs in a formally defined program language i.e. Verilog.
  • Translates them to a machine language representing the execution process.
We take our higher-level language, which will turn into an assembly code, and then we use it as an assembler to turn it into a machine language.

                                                                            figure 4

Physical Synthesis:- 

Actually, this physical synthesis is done after the "floorplan" because we would get specified locations and coordinates info of the macros, blockages, etc. And this would become easy to synthesize as per the following necessary things we already obtained by the floorplan now if any optimization is done on this info basis we would be getting the more precise and highly accurate gate-level netlist structure and reports at this stage.

Post-Synthesis Checks:-
  • Gate level Simulation
  • Formal Verification (i.e. Logic equivalence check)
  • Static Timing Analysis
  • Area, Power estimation

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