ASIC Block level PD flow

 Since a synthesis netlist is provided to us to further start with the PD flow.

Flow-

1. Design Import:-

A stage where we read and required all the inputs like design-wise IPs, IP-wise IPs, Technology wise IPs, etc that we get either from the top-level designer or from the manager level.

create_lib or mw_lib viz a database where it got to be saved related to our design.

2. Sanity Checks:-

It possesses the design checks, timing checks, etc to verify that is their any issues occurring or not because if any kind of error or issues seen or checked over here needed to be resolved here only otherwise it may lead to problems in further steps.

This sanity checks usually verify the SDC, netlist/design (as a check_netlist or check_design), or can also be checked by report_timing also (in the sense of timing if wanted). It also checks the logical library (.lib) and Physical Library (lef) using the command check_library.

        (a) Netlist check- [check_netlist or check_design]

                It checks the quality of the netlist and identifies it as a-

• Floating pins 
• multi-driven nets
• unconstraint pins
• undriven input ports
• unloaded output
• pin mismatch counts

        (b) SDC or check_timing-

• Checks that is their any unconstrained paths or not.
• Clock is reaching all synchronous elements or not.
• is there any multi-driven registers
• check the unconstrainted endpoints
• i/p - o/p delay missing for a port or not

        (c) Library check- To see the mapping is done as per requirements or not.

• Missing cell/pin info
• any duplicate cell

3. Floor planning:-

After sanity checks and confirming it for moving to the pnr flow.

By floor planning, we would be placing the following cells, macros, std. cells with much proper analysis and all care.

        Floor planning is a very crucial step and to be done in such a fine way that all the further steps are done smoothly because of a good floor plan otherwise we are required to come back here again to do floor planning and then further move. 

The objective of floorplan-

• Minimize the area
• Minimize the timing
• Reduce the wire length
• Reduce the IR drop [related to the interconnection length which would lead to the voltage drop]
• Making the routing easy

Note: The kind of physical cells used in this stage are- endcap cells, well tap cells.

4. Power planning:- 

Creating power rails in the base layer. And power given to macros using these straps possesses the Vdd and Vss. So that the macros could get supply from that near to straps. 

Three levels of power distributions-

1. Ring- Vdd and Vss around the chips (also it possesses around the core and macros also as per desired) through the power rings. Usually made at the higher metal layers M8, M9 say
2. Straps- Carries Vdd and Vss from rings across the chips through the vertical and horizontal straps. Usually made at the metal layers M5, M6 say.
3. Rails- Connect Vdd and Vss to the standard cells. Usually, these rails are made at the metal layers M1, M2, M3 say

Note: the kind of physical cells used here is "Decap cells".

5. Pre-Place, Placement and Optimization:-

Pre-place means we put the end cap cells, filler cells, tap cells, io buffers, boundary cells, etc in our design that too after the macros and site row creation, this stage is done before "placement" actually.

Placement- here we place the std. cells in the leftover areas of the core.

If any congestion or any kind of violations came then here it needed an optimization technique to do to meet our target and performance.

Checks after placement are-

• LEC (Logic Equivalence Check)
• Timing- using the command report_qor
• here it usually checks for the setup timing, and
• DRV (that are min. - max cap/trans/etc)
• Congestion analysis

6. CTS and Optimization:-

Clock tree are to be build here. And if there is any kind of latency or skew is been observed in the clock and through the clock-port then we needed to do the optimization.

Checklists are-

• LEC
• clock qor analysis
• timing qor analysis 
• congestion analysis
• clock_skew
• clock_latency

7. Routing and Optimization:-

The signals are been routed in this stage that is after the CTS. [Although we could do both things together under one stage, we should not do it in that way as the clock is highly switching, and the most critical element in the design, so the clock is to be treated separately.] Also after CTS, we can estimate the spaces for allocating our signals in the whole core. 

If any congestion or timing critical issues are been observed then optimizations' are to be required to mitigate it.

Note- Design Finishing means if some cells like filler cells, dummy cells, etc are required to add for future help in optimizations then it will be done here.

Checklists-

• LEC
• timing qor analysis (majorly w.r.t to hold now will be seen, where setup is seen at the placement already)
• DRC 
• congestion

Signoff stage:- This stage is described into three segments-

1. Physical Verifications
1. DRC
2. LVS
3. ERC
2. Power, IR & EM Analysis
3. LEC, RC Extraction & STA

If all the above stages are all clean and clear with effective timing, power, and things requirement then it moves it for "tape out" but if found a small improvement or modification then it goes for ECO.

ECO :-

Eco is nothing but Engineering changing order in this stage fixing all type of issue like drv, setup, hold, Cross talk, etc.

There are two kinds of ECO fixes. 1. timing adjustments; and 2. functional improvements. When it comes to timing fixes, we'll focus on setup, hold, and drc. However, when it comes to functional repairs, adding certain new features to the design (incremental additions) also falls within eco modifications. The netlist will alter in the second situation. For the implementation of eco, we generally prefer primetime (synopsis tool). There are several sorts of commands we will use depending on which one we are modifying in the design, such as violation repairs, drc fixes, power fixes, or any other that the engineer requires. For a better understanding, consult the Primetime user guide.