RC corners

RC interconnect corners  

Firstly, understand the source of variation of r and c that leads to multiple RC corners. Some of the sources are-

1.      Chemical mechanical planarization (CMP) process which removes the excess materials deposited while manufacturing.

2.      Some inconsistencies due to metal etching, where you might etch little bit more or little bit less which can directly impact the thickness of the interconnect wires.

-          RC specifically for the interconnects.

-          Resistance- resistance depends on the length and cross-sectional area. With resistance being directly proportional to wire length, and being inversely proportional to the cross-sectional area. As temperature increases, resistance usually increases.

-          Capacitance- It also depends on the interconnect dimensions and is directly proportional to the cross-section area and inversely proportional to the distance between the two wires.

Note: length is dependent on the design, other parameters are dependent on the technology node (tech file), where minimum wire-pitch, spacing widths are defined in the technology file.

Here, to observe that W and S are inversely corelated means increase in W means smaller in S and vice-versa.

·       If Delay at width W1 < Delay at width W < Delay at width W2, ……... It means your wire lies in “capacitance” dominated region.

·       If Delay at width W1 > Delay at width W > Delay at width W2, ……… it means your wire lies in the resistance dominated region.

This explains how delays of wires changes across RC corners.

We have 4 RC interconnect corners: Cmin, Cmax, RCmin, RCmax.

Ø  RCmax: Although a bad design, but let’s say you have a very long wire (large L) in lower metal layers (which is small W and T) resistance would dominate and you would see the worst delay in the RCmax corner. RCmax is usually the most critical corner for setup timing closure. This would clear when Cc is minimum, and R*Cg is maximum.

Ø  RCmin: Let’s say you have a many min paths in your design, and you’re looking for a best delay number which can potentially result in hold times failures, you would look for RCmin corner, where you have many short nets (R would there be neglegible), and capacitance would be minimum because of maximum spacing (S) and Height (H).

This would usually be the hold critical corner. When Cc is maximum and (R*Cg) is minimum.

Ø  Cmax: In presence of noise, you would want to check the corners with worst coupling capacitance. This would be your Cmax corner. This might also produce the worst delay for short nets for which resistance would be minimum, Cc is maximum.

Ø  Cmin: Cc is minimum, R is maximum, and Cg is minimum. The short nets in min. path with minimal resistance might hold violations.

(reference from- http://vlsi-soc.blogspot.com/2018/11/rc-interconnect-corners_3.html)