ASIC- PD Inputs

 What inputs required for PD engg ?


1. Netlist (.v or .vhd) :- a sequential elements or logical connectivity containing- std. cells, macros, memories, interconnection details, parts of std.cells, macros, etc.

2. Constraints :-  Basically the constraints are divided into two parts-

    (a) Design Rule Constraints :     (from fab obtained)

            - max. capacitance/transitions/fanouts

            - Clock Uncertainties (the deviation of the actual arrival time of the clock edge w.r.t the ideal                       arrival time)

    (b) Optimization constraints : (from designer)

            - timing constraints

            - delay constraints [i/p dela, o/p load, i/p transition, o/p transition, latency]

            - power, area constraints

    (c) SDC (Synopsis Design Constraints) :- (basically related to timing things only so that the data paths works on the basis of clock paths)

            (1) Timing constraints : 

                - clock definition [time period, duty cycle, waveforms]

                - timing exceptions also could be provided [false path, asynchronous path, multicycle path]

            (2) Non-timing constraints :

                - Operating condition (pvt)

                - Wire load model [this is to calculate the interconnect wire delays (RC) and the area                                   overhead (A) due to interconnect]

                - Area, Multi-voltage, power optimization constraints

                - Logic assignments/optimization

                - system interface - DRC

    (d) Clock tree constraints :

            - Root pin definition

            - Insertion delay and skew target

            - Max cap./fanout/transition/inverters for cts

            - no. of buffer lists and levels

Note: We would be able to see the timing constraints, while for power what kinds of constraints or is their or not for power constraints kind of things?

Ans.- Since power is not having any exact command or any specific constraints unlike the timing constraints have. But in some important sections like placement, routings, and CTS we do have the mode settings here in which we can do the optimization for leakage or introduce "efforts" like -effort high" types, etc.

        Although somewhere we use the file named as SAF(Switching activity file) or VCD (Value change dump file).

3. Liberty Timing Files (.lib or .db) :-

        - Timing library

        - std. cell lib, macros lib, io lib

        - Gate delays (viz a function of i/p transition time and o/p load)

Basically it contains-

  • Cell types and functionality
  • Delay models (WLM, NDLM, CSS)
  • Pin/Cell timings
  • design rule
  • PVT condition
  • power details (leakage and dynamic)
4. Library Exchange format (LEF) :- It gives the abstract information whereas the gds will give the detailed information's.
    - cell abstract view
    - Std. Cell LEF/ Macro LEF/ IO LEF

contains-
  • cell name, shape, size, orientations & class of cells
  • port/pin- name and directions
  • layout geometries
  • Blockages info
5. Technology Related Files :-
  • Define units
  • Design rules for layers and vias as per technology (also contains the layer/via capacitance and resistance values as in a lookup table format) 
  • Name, number, physical and electrical parameters of layers and vias. Ex: Direction/Type/Pitch/Width/Offset/Thickness/Resistance/Capacitance/Antenna rules/Max. Metal Density/Blockages details
  • Manufacturing grid definition
  • used for layer parasitic extractions
Note: Technology file has to be loaded before loading other lef files since it hold the layer information for that particular technology.

6. TLU+ file :- It is binary format file that stores the RC coefficients. TLU+ model provides the accurate RC extraction including the effect of width, space, density and temperature on the resistance coefficients.
Main Functions-
  • RC parasitic of metal per unit length
  • These parasitic are used for the calculation of net delays
  • If TLU+ files are not given, then these are extracted from .ITF file
7. Design Exchange formats :- 
(give out the details of all the polynomials used in the design)
    - list and locations of components, vias, pins, nets, special nets
    - die dimensions, row definitions, routing grids, power grids

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