VLSI Knowledge Park

 Since a synthesis netlist is provided to us to further start with the PD flow. Flow- 1. Design Import:- A stage where we read and required all the inputs like design-wise IPs, IP-wise IPs, Technology wise IPs, etc that we get either from the top-level designer or from the manager level. create_lib or mw_lib   viz a database where it got to be saved related to our design. 2. Sanity Checks:- It possesses the design checks, timing checks, etc to verify that is their any issues occurring or not because if any kind of error or issues seen or checked over here needed to be resolved here only otherwise it may lead to problems in further steps. This sanity checks usually verify the SDC, netlist/design (as a check_netlist or check_design ), or can also be checked by report_timing also (in the sense of timing if wanted). It also checks the logical library (.lib) and Physical Library (lef)  using the command check_library.          (a) Netlist check- [che...

 A standard cell library is a collection of well-defined and appropriately characterized logic gates that can be used to implement a digital design by paying attention to the cell height, cell width, voltage rails, well definition, pin placement, and Metal layers, etc. What cells are there in a standard cell library? Combinational logic cells (NAND, NOR INV, etc) variety of drive strengths for all cells complex cells like AOI, OAI, etc Fanin <= 4 Eco cells Since each of them comes with a variety of drive strengths so we have to feed with the output buffers or inverters that are inside the cell i.e. there could be some sort of inverters or buffers or some transistors inside the cell and we provide different widths of these outputs to be able to drive higher and higher output capacitance so we will have lots of those, they are usually called like X1, X2, X3, etc. and so forth it describes the size of the relative size of these cells. Buffers / Inverters Large variety of drive stre...

Logical Synthesis:- Synthesis is the process that converts a RTL into a technology specifying gate-level netlist, optimized for a set of pre-defined constraints. Inputs- rtl design, std. cell library and a set of design constraints Output- a gate-level netlist, mapped to the std. cells library (.lib file) Note: For fpga's: lut, flip flops and RAM blocks are been obtained and given as the inputs in the further steps. Hopefully, it is also efficient in terms of speed, area, power, etc.                                                                                                figure 1 What is Logic Synthesis?                        ...

RTL is a description of a sequential design that possesses data between registers, possibly applying some logic to the data on the way. RTL is the synthesizable subset of an HDL (Verilog, VHDL, System Verilog). But not everything can be implemented in the hardware (i.e. with logic gates). Therefore, only a subset of the HDL is considered "Synthesizable". The Unforgivable Rules- Never put logic on "reset" or the "clock". Never mix reset types. Never create clock domain crossings. Do not infer latches Every "if" has an "Else". Full case settlement LHS for every signal for each condition Assignment (always blocks) In Combinational (always @ *) use blocking (=) assignment In Sequential (always @ posedge) use non-blocking (<=) assignment Always separate the sequential and combinational logic Never assign a signal (LHS) from more than one always blocks 1. No logic on reset (or clock):- The reset and clock signals are not just any signal an...

 It is the logic blocks or circuit layout design which are reusable and describes the implementation of the functionality of hardware within FPGA or ASIC. - IP's are not a physical chips (it is basically a piece of logic which performs the functions of a piece of that hardware over the board). - It is the building blocks of ASIC or FPGA. - It is the intellectual property of one party and can be licensed to another party. Example: Arm based CPU, MALI GPU, USB, I2C, DMA, SPI controller, UART, Multiplexer, Ethernet controller, PCI interface, Power modules, Memory controller, Audio drivers, Video controller, Analog IP such as- ADC, DAC, PLL, etc. Thus, an IP can be analog, digital or mixed signal. IP's are available in 3 form- Soft core, hard core and firm core. 1. Soft Core IP : - It is delivered as synthesizable logic written in Verilog or HDL or available netlist (a list of logic gates and their interconnection). - It is not optimized for the target architecture. So it provides ...