VLSI Knowledge Park

 What inputs required for PD engg ? 1. Netlist (.v or .vhd) :- a sequential elements or logical connectivity containing- std. cells, macros, memories, interconnection details, parts of std.cells, macros, etc. 2. Constraints :-  Basically the constraints are divided into two parts-     (a) Design Rule Constraints :      (from fab obtained)               - max. capacitance/transitions/fanouts               - Clock Uncertainties (the deviation of the actual arrival time of the clock edge w.r.t the ideal                             arrival time)     (b) Optimization constraints : (from designer)               - timing constraints               - delay constraints [i/p dela, o/p load, i/p transitio...

RC interconnect corners   Firstly, understand the source of variation of r and c that leads to multiple RC corners. Some of the sources are- 1.       Chemical mechanical planarization (CMP) process which removes the excess materials deposited while manufacturing. 2.       Some inconsistencies due to metal etching, where you might etch little bit more or little bit less which can directly impact the thickness of the interconnect wires. -           RC specifically for the interconnects. -           Resistance- resistance depends on the length and cross-sectional area. With resistance being directly proportional to wire length, and being inversely proportional to the cross-sectional area. As temperature increases, resistance usually increases. -           Capacitance- It also depends on the ...